View STK672-600_5935935.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

62911hkpc 018-08-0102/71608hkim no. a0755-1/19 STK672-600 overview the STK672-600 is a hybrid ic for use as a unipolar, 2-phase stepping motor driver with pwm current control. applications ? office photocopiers, printers, etc. features ? the motor speed can be controlled by the frequency of an external clock signal. ? 2-phase excitation or 1-2 phase excitation is selected according to switching the state of the mode1 pin (low or high). ? the excitation mode is set at the rising edge of the clock signal when the mode2 pin is high, or at the rising edge or falling edge when the mode2 pin is low. ? the phase is maintained even if the excitatio n mode is switched in the middle of operation. ? the direction of rotation can be changed by applying a high or low signal to the cwb pin used to select the direction of rotation. ? supports schmitt input for 2.5v high level input. ? incorporating a current detection resistor (0.141 : resistor tolerance 2%), motor current can be set using two external resistors. ? equipped with an enable pin that, during clock input, allows motor output to be cut-off and resumed later while maintaining the same excitation timing. ordering number : ena0755a thick-film hybrid ic 2-phase stepping motor driver specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
STK672-600 no. a0755-2/19 specifications absolute maximum ratings at tc = 25 c parameter symbol conditions ratings unit maximum supply voltage 1 v cc max no signal 52 v maximum supply voltage 2 v dd max no signal -0.3 to +7.0 v input voltage v in max logic input pins -0.3 to +7.0 v output current i oh max v dd =5v, clock 200hz 2.65 a allowable power dissipation 1 pdmf max with an arbitrarily large heat sink. per mosfet 7.8 w allowable power dissipation 2 pdpk max no heat sink 3.1 w operating substrate temperature tc max 105 c junction temperature tj max 150 c storage temperature tstg -40 to +125 c allowable operating ranges at ta = 25 c parameter symbol conditions ratings unit operating supply voltage 1 v cc with signals applied 10 to 42 v operating supply voltage 2 v dd with signals applied 5 5% v input high voltage v ih pins 10, 12, 13, 14, 15, 17 2.5 to v dd v input low voltage v il pins 10, 12, 13, 14, 15, 17 0 to 0.6 v output current 1 i oh 1 tc=105 c, clock 200hz, continuous operation, duty=100% 2.0 a output current 2 i oh 2 tc=80 c, clock 200hz, continuous operation, duty=100%, see the motor current (i oh ) derating curve 2.2 a clock frequency f cl minimum pulse width: at least 10 s 0 to 50 khz phase driver withstand voltage v dss i d =1ma (tc=25 c) 100min v recommended operating substrate temperature tc no condensation 0 to 105 c recommended vref range vref tc=105 c 0.14 to 1.38 v refer to the graph for each conduction-period toleranc e range for the output current and brake current. electrical characteristics at tc = 25 c, v cc = 24v, v dd = 5.0v parameter symbol conditions min typ max unit v dd supply current i cco pin 9 current clock=gnd 5.0 9 ma output average current ioave r/l=1 /0.62mh in each phase 0.362 0.402 0.442 a fet diode forward voltage vdf if=1a (r l =23 ) 1.0 1.6 v output saturation voltage vsat r l =23 0.42 0.61 v input leak current i il pins 10, 12, 13, 14, 15, 17 =gnd and 5v 10 a vref input bias current i ib pin 19 =1.0v 204 216 a pwm frequency fc 35 45 56 khz *ioave values are for when the lead frame of the product is soldered to the mounting substrate. notes: a fixed-voltage power supply must be used.
STK672-600 no. a0755-3/19 package dimensions unit:mm (typ) derating curve of motor current, i oh, vs. STK672-600 operating substrate temperature, tc notes ? the current range given above represents conditions wh en output voltage is not in the avalanche state. ? if the output voltage is in the avalanche state, see the allowable avalanche energy for stk672-6** series hybrid ics given in a separate document. ? the operating substrate temperature, tc, given abov e is measured while the motor is operating. because tc varies depending on the am bient temperature, ta, the value of i oh , and the continuous or intermittent operation of i oh , always verify this value using an actual set. 29.2 25.6 (20.47) (5.0) (12.9) (5.6) 1.0 4.2 8.2 (20.4) 0.52 0.4 4.5 119 7.2 14.5 11.0 (5.0) (r1.7) (3.5) 2.0 14.5 14.4 18 1.0=18.0 3.0 0.5 0 080 20 40 60 100 70 10 30 50 90 110 i oh - tc operating substrate temperature, tc- c motor current, i oh - a 2.0 2.5 1.5 1.0 200hz 2 phase excitation hold mode itf02548
STK672-600 no. a0755-4/19 block diagram sample application circuit *: c03 through c08 represents a capacitor recommended for use with a recommended value of 1,000pf. chopper circuit phase excitation signal generator excitation mode selection phase advance counter p.g2 v ss s.g ci bi ai fbb fbo fab fao bb b ab a p.g1 f1 f2 f3 f4 r1 r2 v dd r3 3.9k /1% r4 1.0k /1% v dd =5v mode1 clock cwb enable v ss vref n.c mode2 resetb s.g n.c n.c 19 18 16 15 14 13 12 17 11 10 9 8 7 6 5 4 1 2 3 resetb vref a ab b bb p.g2 24v 10 r03 5.0v c02 d1 cwb mode2 mode1 clock 5.0v p.g1 6 100 15 enable c03 c04 c05 c06 c07 c08 v dd (5v) 16 18 v ss s.g
STK672-600 no. a0755-5/19 precautions [damage to the internal mosfet] ? the resetb pin must be fixed low when applying 5v power. if the resetb pin is allowed to go high at the same time as the 5v power, simultaneous on of the output ph ase will result, causing damage to the internal mosfet. [gnd wiring] ? to reduce noise on the 5v system, be sure to place the gnd of c01 in the circuit given above as close as possible to pin 2 and pin 6 of the hybrid ic. also, to achieve accurate current settings, be sure to connect vref gnd to pin 18 (s.g) used to set the current and to the poi nt where p.g1 and p.g2 share a connection. ? if the driver region v ss pin (pin 16), s.g pin (pin 18), p.g1 pin (pin 2), and p.g2 pin (pin 6) cannot be connected to a single ground, make sure to connect the v ss pin to the control system s.gnd, and the s.g pin to the p.g1 pin and p.g2 pin. [input pins] ? if v dd is not being applied to the hybrid ic, do not apply voltage to input pins 10, 12, 13, 14, 15, or 17. in addition, if v dd is being applied, use care that each input pin does not apply a negative voltage less than -0.3v to v ss , pin 16, and do not apply a voltage greater than or equal to v dd voltage. ? do not wire by connecting the circuit pattern on the p.c.b side to pins 7, 8, or 11 on the n.c. shown in the internal block diagram. ? insert resistor ro3 (47 to 100 ) so that the discharge energy from capacitor co4 is not directly applied to the cmos ic in this hybrid device. if the diode d1 has vf characteristi cs with vf less than or eq ual to 0.6v (when if = 0.1a), this will be smaller than the cmos ic input pin diode vf. if this is the case ro3 may be replaced with a short without problem. ? both ttl and cmos levels are used for the pin 10, 12, 13, 15 and 17 inputs. ? since the input pins do not have built-in pull-up resistors, wh en the open-collector type pins 10, 12, 13, 15, and 17 are used as inputs, a 1 to 15k pull-up resistor (to v dd ) must be used. at this time, use a device for the open collector driver that has output current specifications that pull the voltage down to less than 0.6v at low level (less than 0.6v at low level when i ol =5ma). ? if input pins are connected to gnd (v ss ) using a pull-down resistor, be sure to mount a resistor having a resistance of 120 or less. if designs call for a pull-down resistor having a resistance in the range 120 to 30k , be absolutely sure to mount a 1,000pf capacitor between the input pins and the v ss pin. because sufficient v il cannot be maintained due to the effect of input leak current, i il = 10 a max, do not connect a pull-down resistor having a resistance of 30k or higher. ? the sample application circuit includes a simple reset circu it using d1, r03, c02, and r04. if 5v power rises while voltage still remains in c02, the reset signal cannot be detected as low and the driver may be damaged because on operations result at the same time that driver output is in a or ab phase or b or bb phase. the voltage of c02 must therefore be less than 0.6v when the 5v power rises. in addition, if a resetb signal is to be input based on an external signal such as the clock signal, resetb must always be fixed to a low level when the 5v power signal rises. ? to prevent malfunction due to chopping noise, we recommend that you mount a 1000pf capacitor between pin 16 and each of the input pins 10, 12, 13, 14, 15, and 17. be sure to mount the capa citor as close as possible to the pins of hybrid ic. if input is fixed low, directly connect to pin 16. if input is fixed high, directly connect to the 5v power line. [current setting vref] ? considering the specifications of the vref input bias current, i ib , a value of 1k or less is recommended for r02. ? if the motor current is temporarily reduce d, the circuit given below (STK672-600: i oh >0.2a, stk672-610: i oh >0.3a) is recommended. ? although the driver is equipped with a fixed current control function, it is not equipped with an overcurrent protection function to ensure that the current does not exceed the maximum output current, i oh max. if vref is mistakenly set to a voltage that exceeds i oh max, the driver will be damaged by overcurrent.
STK672-600 no. a0755-6/19 ? motor current peak value i oh setting ? when r02 is open i oh = [vref 1k/1k+3.9k)] rs= (vref 4.9) rs the values 1k and 3.9k repres ent internal driver resistance values, while rs represents the internal driver current detection resistance. vref= (4.9k (4.9k+r01)) 5v (or 3.3v) =i oh 4.9 rs the value 4.9k represents the series resistance valu e of the internal driver values of 1k and 3.9k. ? if r02 is connected i oh = [vref 1k/ (1k+3.9k)] rs= (vref 4.9) rs the values 1k and 3.9k repres ent the internal driver resistance values, while rs represents the in ternal driver current detection resistance. vref= (r0x (r01+r0x)) 5v (or 3.3v) =i oh 4.9 rs = [(4.9k r02) ((4.9k r02) +r01 (4.9k+r02))] 5v(or 3.3v) r0x= (4.9k r02) (4.9k+r02) rs represents the current detection resistance inside the hi c, while the value 4.9k in th e formula above represents the internal resistance valu e of the vref pin. rs=0.141 when using the STK672-600 rs=0.089 when using the stk672-610 input pin functions pin name pin no. function input conditions when operating clock 12 reference clock for motor phase current switchin g operates on the rising edge of the signal (mode2=h) mode1 10 low: 2-phase excitation high: 1-2 phase excitation mode2 17 excitation mode selection high: rising edge low: rising and falling edge cwb 13 motor direction switching low: cw (forward) high: ccw (reverse) resetb 14 system reset and a, ab , b, and bb outputs cutoff. applications must apply a reset signal for at least 10 s when v dd is first applied. a reset is applied by a low level enable 15 the a, ab, b, and bb outputs are turned off, and after operation is restored by returning the enable pin to the high level, operation continues with the same excitation timing as before the low-level input. the a, ab, b, and bb outputs are turned off by a low- level input. (1) a simple reset function is formed from d1, co4, ro3, and ro4 in this application circuit. with the clock input held low, when the 5v supply voltage is brought up a reset is applied if the motor output phases a and bb are driven. if the 5v supply voltage rise time is slow (over 50ms), the motor output phases a and bb may not be driven. increase the value of the capacitor co 2 and check circuit operation again. (2) see the timing chart for the concrete details on circuit operation. 5v r01 r02 r3 5v r01 r02 r3 vref vref i oh 0
STK672-600 no. a0755-7/19 timing charts 2-phase excitation 1-2 phase excitation mode1 resetb cwb clock enable fao fab fbo fbb mode2 mode1 resetb cwb clock enable fao fab fbo fbb mode2
STK672-600 no. a0755-8/19 1-2 phase excitation (cwb) 2-phase excitation switch to 1-2 phase excitation mode1 resetb cwb clock enable fao fab fbo fbb mode2 mode1 resetb cwb clock enable fao fab fbo fbb mode2
STK672-600 no. a0755-9/19 1-2 phase excitation (enable) 1-2 phase excitation (hold operation results during fixed clock) mode1 resetb cwb clock enable fao fab fbo fbb mode2 hold operation mode1 resetb cwb clock enable fao fab fbo fbb mode2
STK672-600 no. a0755-10/19 2-phase excitation (mode2) 1-2 phase excitation (mode2) mode1 resetb cwb clock enable fao fab fbo fbb mode2 mode1 resetb cwb clock enable fao fab fbo fbb mode2
STK672-600 no. a0755-11/19 usage notes 1. STK672-600 and stk672-610 input signal functions and timing (all inputs have no internal pull-up resistor and are ttl level schmitt trigger inputs.) [resetb and clock (input signal timi ng when power is first applied)] as shown in the timing chart, a resetb signal input is requ ired by the driver to operate with the timing in which the f1 gate is turned on first. the resetb signal timing must be set up to have a width of at least 10 s, as shown below. the capacitor co2, and the resistors ro3 and ro4 in the app lication circuit form simple reset circuit that uses the rc time constant rising time. however, when designing the resetb input based on v ih levels, the application must have the timing shown in figure. resetb and clock signals input timing [clock (phase switching clock)] ? input frequency: dc to 50khz ? minimum pulse width: 10 s ? mode2=1(high) signals are read on the rising edge. ? mode2=0(low) signals are read on the rising and falling edges. [cwb (motor direction setting)] the direction of rotation is switched by setting cwb to 1 (hig h) or 0 (low). see the timing charts for details on the operation of the outputs. note: the state of the cwb input must not be changed during the 6.25 s period before and after the rising edge of the clock input. [enable (forcible on/off control of the a, ab, b, and bb outputs, and hybrid ic internal operation)] enable=1: normal operation enable=0: outputs a, ab, b, an d bb forced to the off state. if, during the state where clock signal input is provid ed, the enable pin is set to 0 and then is later restored to the 1 state, the ic will resume opera tion with the excitation timing continued from before the point enable was set to 0. if sudden stop is applied to the clock signal used for motor rotation, the motor axis may advance beyond the theoretical position due to inertia. to stop at the theore tical position, the slow down setting for gradually slowing the clock cycle is required. enable must be initially set high for input as shown in the timing chart. [mode1 and mode2 (excitation mode selection)] mode1=0: 2-phase excitation mode2=1: rising edge of clock mode1=1: 1-2 phase excitation mode2=0: rising and falling edges of clock see the timing charts for details on output operation in these modes. note: the state of the mode input must not be changed during the 5 s period before and after the rising edge of the clock input. rise of the 5v supply voltage resetb signal input clock signal a t least 10
STK672-600 no. a0755-12/19 2. calculating STK672-600 hic internal power loss the average internal power loss in each excitation mode of the STK672-600 can be calculated from the following formulas. each excitation mode 2-phase excitation mode 2pdavex= (vsat+vdf) 0.5 clock i oh t2+0.5 clock i oh (vsat t1+vdf t3) 1-2 phase excitation mode 1-2pdavex= (vsat+vdf) 0.25 clock i oh t2+0.25 clock i oh (vsat t1+vdf t3) motor hold mode holdpdavex= (vsat+vdf) i oh vsat: combined voltage represented by the ron voltage drop+shunt resistor vdf: combined voltage represented by the mosfet body diode+shunt resistor clock: input clock (clock pin signal frequency) t1, t2, and t3 represent the waveforms shown in the figure below. t1: time required for the winding cu rrent to reach the set current (i oh ) t2: time in the constant current control (pwm) region t3: time from end of phase input signal until inverse current regeneration is complete motor com current waveform model t1= (-l/(r+0.42)) in (1-((r+0.42)/v cc ) i oh ) t3= (-l/r) in ((v cc +0.42)/(i oh r+v cc +0.42)) v cc : motor supply voltage (v) l: motor inductance (h) r: motor winding resistance ( ) i oh : motor set output current crest value (a) relationship of clock, t1, t2, and t3 in each excitation mode 2-phase excitation mode: t2= (2/clock) - (t1+t3) 1-2 phase excitation mode: t2= (3/clock) -t1 for vsat and vdf, be sure to substitute values from the graphs of vsat vs. i oh and vdf vs. i oh while the set current value is i oh . then, determine whether a heat sink is re quired by comparing with the graph of tc vs. pd based on the average hic power loss calculated. when designing a heat sink, refer to the section ?thermal design? found on the next page. the average hic power loss, pdav, described above does not have the avalanche?s loss. to include the avalanche?s loss, be sure to add equation (2), ?stk676-6** allowable avalanche energy valu e? to pdav above. when using this ic without a fin always check for temperature increases in the set, because the hic substrate temper ature, tc, varies due to effects of convection around the hic. i oh 0a t1 t2 t3
STK672-600 no. a0755-13/19 STK672-600 output saturation voltage, vsat - output current, i oh STK672-600 forward voltage, vdf -output current, i oh substrate temperature rise , tc(no heat sink) - internal av erage power dissipation, pdav 0 0.5 1.0 1.5 3.0 2.5 2.0 0.4 0.2 0 vsat - i oh output current, i oh - a output saturation voltage, vsat - v 1.4 1.0 1.2 0.8 0.6 2 5 c 1 0 5 c itf02549 0 0.5 1.0 1.5 3.0 2.5 2.0 0.4 0.2 0 vdf- i oh output current, i oh - a forward voltage, vdf - v 1.4 1.0 1.2 0.8 0.6 2 5 c 1 0 5 c itf02550 80 20 10 0 0 1.0 2.0 3.0 3.5 0.5 1.5 2.5 tc - pdav hybrid ic internal average power dissipation, pdav - w substrate temperature rise, tc - c 50 70 60 40 30 itf02551
STK672-600 no. a0755-14/19 3. STK672-600 allowable avalanche energy value (1) allowable range in avalanche mode when driving a 2-phase stepping motor with constant current chopping using an stk672-6** series hybrid ic, the waveforms shown in figure 1 belo w result for the output current, i d , and voltage, v ds . figure 1 output current, i d , and voltage, v ds , waveforms 1 of the stk672-6** series when driving a 2-phase stepping motor with constant current chopping when operations of the mosfet built into stk672-6** seri es ics is turned off for constant current chopping, the i d signal falls like the waveform shown in the figure above. at this time, the output voltage, v ds , suddenly rises due to electromagnetic induction generated by the motor coil. in the case of voltage that rises suddenly , voltage is restricted by the mosfet v dss . voltage restriction by v dss results in a mosfet avalanche. during avalanche operations, i d flows and the instantaneous energy at this time, eavl1, is represented by equation (1). eavl1=v dss iavl 0.5 tavl ------------------------------------------- (1) v dss : v units, iavl: a units, tavl: sec units the coefficient 0.5 in equation (1) is a constant required to convert the iavl triangle wave to a square wave. during stk672-6** series operations, the waveforms in the figure above repeat due to the constant current chopping operation. the allowable avalanche energy, eavl, is therefore represented by equation (2) used to find the average power loss, pavl, during avalanche mode multiplied by the chopping frequency in equation (1). pavl=v dss iavl 0.5 tavl fc ------------------------------------------- (2) fc: hz units (fc is set to the pwm frequency of 50khz.) for v dss , iavl, and tavl, be sure to actually operate th e stk672-6** series and substitute values when operations are observed using an oscilloscope. ex. if v dss =110v, iavl=1a, tavl=0.2 s when using a STK672-600 driver, the result is: pavl=110 1 0.5 0.2 10 -6 50 10 3 =0.55w v dss =110v is a value actually measured using an oscilloscope. the allowable loss range for the allowable avalanche ener gy value, pavl, is shown in the graph in figure 3. when examining the avalanche energy, be sure to actually drive a motor and observe the i d , v dss , and tavl waveforms during operation, and then check that the result of calculating equation (2) falls within the allowable range for avalanche operations. v dss : voltage during avalanche operations i oh : motor current peak value iavl: current during avalanche operations tavl: time of avalanche operations v ds i d itf02557
STK672-600 no. a0755-15/19 (2) i d and v dss operating waveforms in non-avalanche mode although the waveforms during avalanche mode are given in figure 1, sometimes an avalanche does not result during actual operations. factors causing avalanche are listed below. ? poor coupling of the motor?s phase coils (electromagnetic coupling of a phase and ab phase, b phase and bb phase). ? increase in the lead inductance of the harness caused by the circuit pattern of the p.c. board and motor. ? increases in v dss , tavl, and iavl in figure 1 due to an increase in the supply voltage from 24v to 36v. if the factors above are negligible, the waveforms shown in figure 1 become waveforms without avalanche as shown in figure 2. under operations shown in figure 2, avalanche does not occur and there is no need to consider the allowable loss range of pavl shown in figure 3. figure 2 output current, i d , and voltage, v ds , waveforms 2 of the stk672-6** series when driving a 2-phase stepping motor with constant current chopping figure 3 allowable loss range, pavl-i oh during STK672-600 avalanche operations note: the operating conditions given above represent a loss when driving a 2-phase stepping motor with constant current chopping. because it is possible to apply 2.8w or more at i oh =0a, be sure to avoid using the mosfet body diode that is used to drive the motor as a zener diode. i oh : motor current peak value v ds i d itf02558 0 0.5 1.0 1.5 2.5 2.0 1.0 0.5 0 pavl - i oh 5.0 3.5 4.0 4.5 2.5 3.0 2.0 1.5 8 0 c 1 0 5 c average power loss in the avalanche state, pavl- w motor phase current, i oh - a itf02552
STK672-600 no. a0755-16/19 4. thermal design [operating range in which a heat sink is not used] use of a heat sink to lower the operating substrate temperat ure of the hic (hybrid ic) is effective in increasing the quality of the hic. the size of heat sink for the hic varies depending on the magnitude of the average power loss, pdav, within the hic. the value of pdav increases as the output current in creases. to calculate pdav, refer to ?calculating internal hic loss for the STK672-600 and stk6 72-610? in the specification document. calculate the internal hic loss, pdav, assuming repeat operation such as shown in figure 1 below, since conduction during motor rotation and off time both exist during actual motor operations, figure 1 motor current timing t1: motor rotation operation time t2: motor hold operation time t3: motor current off time t2 may be reduced, depending on the application. t0: single repeated motor operating cycle i o 1 and i o 2: motor current peak values due to the structure of motor windings, the phase current is a positive and negative current with a pulse form. note that figure 1 presents the concepts here, and that the on/off duty of the actual signals will differ. the hybrid ic internal average power dissipation pdav can be cal culated from the following formula. pdav= (t1 p1+t2 p2+t3 0) to ---------------------------- (i) (here, p1 is the pdav for i o 1 and p2 is the pdav for i o 2) if the value calculated using equation (i) is 1.5w or less, and the ambient temperature, ta, is 60 c or less, there is no need to attach a heat sink. refer to figure 2 for operating substrate temperature data when no heat sink is used. [operating range in which a heat sink is used] although a heat sink is attached to lower tc if pdav in creases, the resulting size can be found using the value of c-a in equation (ii) below and the graph depicted in figure 3. c-a= (tc max-ta) pdav ---------------------------- (ii) tc max: maximum operating substrate temperature =105 c ta: hic ambient temperature although a heat sink can be designed based on equations (i) and (ii) above, be sure to mount the hic in a set and confirm that the substrate temperature, tc, is 105 c or less. the average hic power loss, pdav, described above represents the power loss when there is no avalanche operation. to add the loss during avalanche operations, be sure to add equation (2), ?allowa ble stk672-6** avalanche energy value?, to pdav. i o 1 i o 2 -i o 1 0a t1 t2 t3 t0 motor phase current (sink side)
STK672-600 no. a0755-17/19 figure 2 substrat e temperature rise, tc(no heat sink) - internal av erage power dissipation, pdav figure 3 heat sink area (board thickness: 2mm) - c-a 5. mitigated curve of package power loss, pdpk, vs. ambient temperature, ta package power loss, pdpk, refers to the average internal power loss, pdav, allowable without a heat sink. the figure below represents the allowable power loss, pd pk, vs. fluctuations in the ambient temperature, ta. power loss of up to 3.1w is allowable at ta=25 c, and of up to 1.75w at ta=60 c. allowable power dissipation, pdpk(no heat sink) - ambient temperature, ta 80 20 10 0 0 1.0 2.0 3.0 3.5 0.5 1.5 2.5 tc - pdav hybrid ic internal average power dissipation, pdav - w substrate temperature rise, tc - c 50 70 60 40 30 itf02553 2 1.0 2 100 7 10 35 2 7 35 1000 c-a - s heat sink area, s - cm 2 heat sink thermal resistance, c-a - c/w 5 100 3 10 7 2 5 3 7 w i t h n o s u r f a c e f i n i s h w i t h a f l a t bl a c k s ur f a c e f i ni s h itf02554 1.0 0.5 0 080 20 40 60 100 120 pdpk - ta ambient temperature,ta - c allowable power dissipation, pdpk - w 2.5 3.0 3.5 2.0 1.5 itf02511
STK672-600 no. a0755-18/19 6. example of stepping motor driver out put current path (1-2 phase excitation) chopper circuit phase excitation signal generator excitation mode selection phase advance counter p.g2 mode1 mode2 clock cwb resetb enable v ss s.g ci bi ai fbb fbo fab fao bb b ab a p.g1 f1 f2 f3 f4 r1 r2 v dd r3 3.9k r4 1.0k + 24v p.gnd c02 at least 100
STK672-600 no. a0755-19/19 ps this catalog provides informati on as of june, 2011. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rat ed values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-quality high-reliab ility products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accidents or events that c ould endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descr ibed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any oth er rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from th e use of the technical information and products mentioned above. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export contro l laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

▲Up To Search▲

Price & Availability of STK672-600

	To Download STK672-600 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .